GX3702

GX3702 Specifications

Digital I/O Channels
Number of Channels	160 I/O signals, up to 84 I/O can be configured as 42 differential I/O channels, 4 I/O are single-ended or 2 differential clock inputs
Logic Families	LVTTL, LVDS, configurable for 1.2 / 2.5 / 3.3 V logic; 5 V compatible
Output Current	± 12 mA
Input Leakage Current	±10 µA
Power on State	Default is disconnect at power on (unprogrammed FPGA) or defined by FPGA program
Protection	Overvoltage: -0.5 V to 7.0 V (input) Short circuit: up to 8 outputs may be shorted at a time
Connector	(4) SCSI III, VHDCI type, 68 pin female
Expansion Board Interface
Board ID	4 bits
External Digital I/O Interface	160 I/O
Master Clear	From PXI interface
Power	±12 V, +5 V, +3.3 V, +2.5 V, +1.2 V
I/O Connector	±12 V, +5 V, +3.3 V, +2.5 V, +1.2 V
Timing Sources
PXI Bus	10 MHz
Internal	80 MHz oscillator, ±20 ppm
FPGA and Memory
FPGA Type	Altera Stratix III, EP3SL50F780
Number of PLLs	Four
Logic Elements	47.5 K
Internal Memory	1.836 Mb
On-Board Memory	256 K x 32 SSRAM
On-Board Flash	16 MB

Power
(Actual power is dependent on the specific FPGA and expansion board design)
3.3 VDC	3.6 A (typ); 4.9 A (max)
5 VDC	0.045 A (max)
12 VDC (For Expansion Board)	Expansion board dependent
Environmental
Operating Temperature	0 °C to +50 °C
Storage Temperature	-20 °C to +70 °C
Size	3U PXI
Weight	200 g

Note: Specifications are subject to change without notice.

The GX3702 is a user configurable, FPGA-based, 3U PXI card which offers 160 digital I/O signals which can be configured for single-ended or differential interfaces. The card employs the Altera Stratix III FPGA, which can support SerDes data rates up to 1.2 Gb/s, digital I/O clock rates of 700 MHz, and features over 45,000 logic elements and 1.836 Kb of memory. The GX3702 is supplied with an integral expansion board providing access to the FPGA’s 160 I/Os and is pin for pin compatible with the NI PXI 7811R and 7813R FPGA cards . Alternatively, users can design their own custom expansion cards for specific applications – eliminating the need for additional external boards which are cumbersome and physically difficult to integrate into a test system. The design of the FPGA is done by using Altera’s free Quartus II Web Edition tool set. Once the user has compiled the FPGA design, the configuration file can be loaded into the FPGA directly or via an on-board EEPROM.

Features

The GX3702’s digital I/O signals are 5 V tolerant. Logic families supported by the I/O interface include LVTTL, LVDS and LVCMOS. The FPGA device supports up to four phase lock loops for clock synthesis, clock generation and for support of the I/O interface. An on-board 80 MHz oscillator is available for use with the FGPA device or alternatively, the PXI 10 MHz clock can be used as a clock reference by the FPGA.

The FPGA has access to all of the PXI bus resources including the PXI 10 MHz clock, the local bus, and the PXI triggers; allowing the user to create a custom instrument which incorporates all PXI bus resources. Control and access to the FPGA is provided via the GX3702’s driver which includes DMA and interrupt support tools for downloading the compiled FPGA code as well as register read and write functionality.

Programming and Software

The board is supplied with the GxFPGA library, a software package that includes a virtual instrument panel, and a Windows 32/64-bit DLL driver library and documentation. The virtual panel can be used to interactively program and control the instrument from a window that displays the instrument’s current settings and status. In addition, interface files are provided to support access to programming tools and languages such as ATEasy, LabView, LabView/Real-Time, C/C++, Microsoft Visual Basic®, Delphi, and Pascal. An On-Line help file and PDF User’s Guide provides documentation that includes instructions for installing, using and programming the board.
A separate software package – GtLinux – provides support for Linux 32/64 operating systems.