GX5290 Series Specifications
GX5291
| Input / Output Channel Features | |
|---|---|
| Data Direction Control | Dynamically controlled on a per vector and per channel basis |
| Channels Per Board | 32 |
| Channel Configuration Per Board (Software Controlled) |
32 / 16 / 8 / 4 / 2 / 1 |
| Maximum Number Channels per Domain | 32 |
| Logic Families | TTL/LVTTL/CMOS/LVCMOS (1.5 V, 1.8 V, 2.5 V, 3.3 V, or 5 V compatible) |
| I/O Levels | TTL/LVTTL/CMOS/LVCMOS: Programmable Output Voltage Level 1.4 V (Min); 3.6 V (Max) Input Threshold (selectable) 1.5 V, 1.8V, 2.5V, or 3.3 V (5V tolerant) Supports standard logic levels Recommended Operating Conditions 0V (Min); 5.5V (Max) |
| Memory Depth Per Channel | 32 Mb – 1Gb, programmable |
| Channel Timing Skew | ± 1 nS |
| Timing | |
| Internal Test Clock (PLL) | |
| Frequency Range | 5 Hz (Min.); 100 MHz (Max.), GX5291-100 50 MHz (Max.), GX5291-50 |
| Accuracy | Greater of (±1Hz or ±0.02% of programmed value) + accuracy of reference clock (PXI 10 MHz or external reference clock) |
| Jitter | ±20 mUI of internal clock frequency, max |
| Reference | PXI 10 MHz clock or XClk (external clock) input |
| Internal B Clock Output (TTL / LVTTL) | |
| Frequency Range | 300 KHz (Min.); 100 MHz (Max.), GX5291-100 50 MHz (Max), GX5291-50 |
| Accuracy | Greater of (±1 Hz or ±0.5% of programmed value) + accuracy of the reference clock |
| Internal Strobe (OSTB) and Output Clock (OCLK) Outputs, Clock and Data Timing | |
| Logic Levels | TTL / LVTTL / CMOS / LVCMOS, programmable output voltage level, 1.4 V (min) to 3.6 V (max) |
| Frequency | Internal clock or External strobe, External clock inputs |
| Programmable Delays (Using Internal Clock Source Only) For Internal Strobe and Output Clock Signals | 0 – 27nS in 250pS steps (5 Hz to 100 MHz), GX5291-100 0 – 27nS in 250pS steps (5 Hz to 50 MHz),, GX5292-50 |
| Output Clock to Data Output Delay | __nS, active OCLK clock edge to valid data |
| Strobe Clock to Data Input | __nS data setup time (min) __nS data hold time (min) Relative to OSTB clock edge |
| External Test Clock Input | |
| Frequency Range (Configured as Sample Clock) | 0 Hz (Min.); 100 MHz (Max.), GX5291-100 0 Hz (Min.); 50 MHz (Max.),, GX5291-50 |
| Frequency Range (Configured as Reference Clock to PLL) | 8MHz to 10.5 MHz |
| Pulse Width | 40% min, 60% max |
| Input Logic Levels | User selectable I/O level, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, (5 V tolerant), TTL, / LVTTL / CMOS, / LVCMOS |
| External Strobe Clock Input | |
| Frequency Range | 0 to 100MHz , GX5291-100 0 to 50 MHz, GX5291-50 |
| Logic Levels | TTL / LVTTL / CMOS / LVCMOS Input threshold: 1.5 V, 1.8 V, 2.5 V, or 3.3 V (5 V tolerant) |
| External Status & Control Signals | |
| Logic Levels | TTL/LVTTL/CMOS/LVCMOS: Prog. Output Voltage Level: 1.4 V (Min); 3.6 V (Max) Input Threshold: 1.5 V, 1.8 V, 2.5 V, or 3.3 V (5 V tolerant) |
| Trigger Source | Software, PXI trigger bus, External event, External trigger input (overrides Run command) |
| External Clock Enable | Internal (software) or External input (via J3 connector) |
| External Strobe Enable | Internal (software) or External input (via J3 connector) |
| External Event Bus | 16 input lines with mask and logic AND conditioning |
| Pause | External pause input overrides Pause command |
| Pause Latency | 10 clock cycles to acquire data after pause deasserts |
| Run | Run status indicator (J3 connector) |
| Power | |
|---|---|
| 3.3 VDC | 200 mA (min); 4 A (max) |
| 5 VDC | 50 mA (min); 2 A (max) |
| 12 VDC | 0.03 mA (min); 0.1 mA (max) |
| Front Panel Connectors | |
| J1 | I/O TTL Signals, 68-pin VHD connector |
| J3 | Timing/Status Signals, 68-pin VHD connector |
| J4 | Control Signals, 68-pin VHD connector |
| Environmental | |
| Operating Temperature | 0 °C to 50 °C |
| Storage Temperature | -20 °C to 70 °C |
| Size | 3U PXI |
| Weight | 200 g |
GX5292
| Input / Output Channel Features | |
|---|---|
| Logic Families | TTL/LVTTL/CMOS/LVCMOS (1.5 V, 1.8 V, 2.5 V, 3.3 V, or 5 V), LVDS/LVDM/M-LVDS |
| I/O Levels | TTL/LVTTL/CMOS/LVCMOS: Programmable Output Voltage Level 1.4 V (Min); 3.6 V (Max) Input Threshold 1.5 V, 1.8V, 2.5V, or 3.3 V (5V tolerant) Recommended Operating Conditions 0 V (Min); 5.5 V (Max) LVDS/LVDM/M-LVDS: Recommended Operating Conditions Voltage Output: -1.4 V (Min.); 3.8 V (Max.) Voltage Input: .05 V (Min.); 3.3 V (Max.) |
| Memory Depth Per Channel | 64 MB – 2 GB |
| Number of Channels | 32 I/O, direction and configuration is dynamically configurable on a per vector and per channel basis |
| Maximum Number Channels per Domain | 256 |
| Channel Timing Skew | 1 ns same card, 1 ns between cards |
| Test Modes | |
|---|---|
| Stimulus / Response | Drive / capture data, up to 64 Mb per channel |
| Real-Time Compare | Drive / compare data against expected data pattern Expect & mask data on a per cycle basis |
| Real Time Compare Record Memory | 1024 x 64 bits of record memory Records compared data and address |
| Real Time Compare Stop Modes | Stop on defined count errors ( max is 1024) Stop when detected failures equal the defined number of failures Stop on defined comparison data value Stop on defined program counter value |
| Timing | |
| Internal Test Clock (PLL) | |
| Frequency Range | 5 Hz (Min.); 100 MHz (Max.) |
| Accuracy | Greater of (±1Hz or ±0.02% of programmed value) + accuracy of reference clock (PXI 10 MHz or external reference clock) |
| Jitter | ±20 mUI of internal clock frequency, max |
| Reference | PXI 10 MHz clock or XClk (external clock) input |
| Internal B Clock Output (TTL / LVTTL) | |
| Frequency Range | 300 KHz (min); 100 MHz (max) |
| Accuracy | Greater of (±1 Hz or ±0.5% of programmed value) + accuracy of the reference clock |
| Internal C Clock Output (LVDS/LVDM/MOLVDS) | |
| Frequency Range | 300KHz (min); 100 MHz (max) |
| Accuracy | Greater of (±1 Hz or ±0.5% of programmed value) + accuracy of reference clock |
| External Test Clock Input | |
| Frequency Range (Configured as Sample Clock) | 0 Hz (min); 100 MHz (max) |
| Frequency Range (Configured as Input to PLL) | 8MHz (min) to 10.5 MHz (max) |
| Pulse Width | 40% min, 60% max |
| Input Level | User selectable I/O level: 1.5 V, 1.8 V, 2.5 V, or 3.3 V (5 V tolerant) |
| External Strobe Clock Input | |
| Frequency Range | 0 Hz (min); 100 MHz (max) |
| Logic Levels | TTL/LVTTL/CMOS/LVCMOS: Prog. Output Voltage Level: 1.4 V (Min); 3.6 V (Max) Input Threshold: 1.5 V, 1.8V, 2.5V, or 3.3 V (5V tolerant) |
| External Status & Control Signals | |
| Logic Levels | TTL/LVTTL/CMOS/LVCMOS: Prog. Output Voltage Level: 1.4 V (Min); 3.6 V (Max) Input Threshold: 1.5 V, 1.8 V, 2.5 V, or 3.3 V (5 V tolerant) |
| Trigger Source | Software, PXI trigger bus, External event, External trigger input (overrides Run command) |
| External Clock Enable | Internal (software) or External input (via J3 connector) |
| External Strobe Enable | Internal (software) or External input (via J3 connector) |
| External Event Bus | 16 input lines with mask and logic AND conditioning |
| Pause | External pause input overrides Pause command |
| Pause Latency | 10 clock cycles to acquire data after pause deasserts |
| Run | Run status indicator (J3 connector) |
| Power | |
| 3.3 VDC | 200 mA (min); 4 A (max) |
| 5 VDC | 50 mA (min); 2 A (max) |
| 12 VDC | 0.03 mA (min); 0.1 mA (max) |
| Front Panel Connectors | |
| J1 | I/O TTL Signals, 68-pin VHD connector |
| J2 | I/O LVDS Signals, 68-pin VHD connector |
| J3 | Timing Signals, 68-pin VHD connector |
| J4 | Control Connector, 68-pin VHD connector |
| Environmental | |
| Operating Temperature | 0 °C to 50 °C |
| Storage Temperature | -20 °C to 70 °C |
| Size | 3U PXI |
| Weight | 200 g |
GX5293
| Input / Output Channel Features | |
|---|---|
| Logic Families | LVTTL/CMOS/LVCMOS (1.5 V, 1.8 V, 2.5 V, or 3.3 V) , LVDS/LVDM/M-LVDS |
| I/O Levels | LVTTL/CMOS/LVCMOS: Programmable Output Voltage Level 1.4 V (Min); 3.6 V (Max) Input Threshold 1.5 V, 1.8V, 2.5V, or 3.3 V Recommended Operating Conditions 0V (Min); 3.6V (Max) LVDS/LVDM/M-LVDS: Recommended Operating Conditions Voltage Output: -1.4V (Min.); 3.8 V (Max.) Voltage Input: .05V (Min.); 3.3V (Max.) |
| Memory Depth Per Channel | 128 MB |
| Number of Channels | 16 I/O, direction and configuration is dynamically configurable on a per vector and per channel basis 32 I/O, for vector rates <100 MHz |
| Maximum Number Channels per Domain | 256 |
| Timing | |
| Internal Test Clock | |
| Frequency Range | 5 Hz (min); 200 MHz (max) |
| Resolution | Greater of 1 Hz or .5% |
| Internal B Clock Output (TTL / LVTTL) | |
| Frequency Range | 300 KHz (min); 200 MHz (max) |
| Resolution | Greater of 1 Hz or .5% |
| Internal C Clock Output (LVDS/LVDM/MOLVDS) | |
| Frequency Range | 300KHz (min); 200 MHz (max) |
| Resolution | Greater of 1 Hz or .5% |
| External Clock Input | |
| Direct | 0 Hz (min); 200 MHz (max) |
| PLL | 3 MHz (min) 200 MHz (max) |
| Pulse Width | 40% min, 60% max |
| Input Level | User selectable I/O level: 1.5 V, 1.8 V, 2.5 V, or 3.3 V |
| Power | |
| 3.3 VDC | 200 mA (min); 4 A (max) |
| 5 VDC | 50 mA (min); 2 A (max) |
| 12 VDC | 0.03 mA (min); 0.1 mA (max) |
| Environmental | |
|---|---|
| Operating Temperature | 0 °C to 50 °C |
| Storage Temperature | -20 °C to 70 °C |
| Size | 3U PXI |
| Weight | 200 g |
Note: Specifications are subject to change without notice.
