Overview

The PulseBlasterESR MultiCore 8M series utilizes multiple PulseBlaster Cores implemented on a new series of PulseBlasterESR PCI boards. The MultiCore designs uses multiple proprietary PulseBlaster processor cores, specially designed for MultiCore operation on a single chip. These new designs allows the user to program and run independent programs on each core, up to 8388608 (8M) instructions in total, in parallel, while maintaining precise timing synchronization between the cores. At 500 MHz, these designs allow for 2.0 ns timing resolution.

All cores are driven by the same, single clock source. They can be synchronized to start at the same time and run two unique pulse programs/sequences concurrently. At 500 MHz, the available resolution of each pulse/delay/interval is 2.0 ns (one clock cycle), the minimum pulse/delay/interval length is 18 clock cycles, or 36.0 ns, and the maximum pulse/delay/interval length is 230clock cycles (~1.07 s). The 500MHz PulseBlasterESR MultiCore 8M has a total of 8M instruction memory words equally divided between cores. This equates to 4M instructions per Core for DualCore designs, and 2M instructions per core for QuadCore Designs.