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8051 IP Core

  • OP Code Compatibility: The IP core is fully compatible with the original Intel 8051 device’s OP codes, ensuring seamless code compatibility with existing 8051 software.
  • Optimized Command Execution: With a new architecture, the IP core delivers faster command execution, enhancing overall system performance.
  • Efficiency in Command Execution: All commands are executed in 1-4 clock cycles, depending on the number of operands, optimizing command processing and responsiveness.
  • Flexible Parameterization: The IP core offers flexibility by allowing users to adjust the number of timer and UART units to meet the specific needs of their application.
  • Verified Compatibility: The IP core’s compatibility has been rigorously tested through extensive simulations, providing confidence in its alignment with the 8051 standard, although it is offered without a guarantee.
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Key Features of the Oregano Systems 8051 IP Core:

  • Fully Synchronous Circuit Design: The IP core is designed to operate with full synchrony, ensuring precise and reliable execution of commands.
  • Single Clock Operation: The entire core operates using a single clock, simplifying the system’s timing and synchronization.
  • Synthesizable Circuit Description: The IP core is provided as a synthesizable circuit description in VHDL, making it ready for integration into your FPGA or ASIC designs.
  • OP Code Compatibility: It is fully OP code compatible with the original Intel 8051 device, ensuring seamless code compatibility with existing 8051 software.
  • Enhanced Command Execution: The IP core boasts faster command execution due to its optimized architecture, offering improved performance.
  • Efficient Command Execution: All commands are executed in 1-4 clock cycles, with execution time dependent on the number of operands, optimizing system performance.
  • Separate RAM and ROM Data/Address Bus: The IP core features distinct data and address buses for RAM and ROM, facilitating efficient data access.
  • Parameterizable Timer and UART Units: Users have the flexibility to parameterize the number of timer and UART units, tailoring the core to the specific application’s requirements.
  • Flexible Multiplier and Divider Units: The IP core supports both conventional multiplying and dividing algorithms as well as fast parallel multiplier and divider units, providing options for various computation needs.
  • Compatibility Verification: The IP core’s compatibility has been extensively verified through simulations, ensuring that it aligns with the 8051 standard. However, it is provided without a guarantee.

The 8051 IP Core, a collaborative development with the Vienna University of Technology, is designed to maintain binary compatibility with Intel’s well-established 8051 processor. Oregano Systems’ 8051 IP Core is available as a parameterizable, synthesizable VHDL circuit description.

This IP Core offers enhanced program execution speed when compared to original 8051 devices, thanks to an optimized processor architecture. Furthermore, the Oregano Systems 8051 IP Core is fully parametrizable to meet specific application requirements. Notably, it is available free of charge, even for industrial applications, under the LGPL (Lesser General Public License).

We kindly request your feedback on your successful implementation of the Oregano Systems 8051 IP Core in your FPGA or ASIC design. You can share your experience with us by sending a brief email description or by utilizing the provided 8051 IP Core feedback form (PDF-File). Your input is valuable to us as we continue to enhance and optimize our IP core solutions.

The Oregano Systems 8051 IP Core is an IP core that is fully compatible with the 8051 architecture. It has been meticulously designed and optimized to meet the specific requirements of a System-on-Chip (SoC) design flow. Here are the notable release versions of the 8051 IP Core:

  • Release Version 1.3 (September 2002): This version marked the initial release of the 8051 IP Core, providing a solid foundation for integrating 8051-compatible functionality into SoC designs.
  • Release Version 1.4 (August 2004): With this release, the 8051 IP Core received enhancements and improvements, likely addressing feedback and evolving design needs in the industry.
  • Release Version 1.6 (June 2013): The 1.6 release represented a significant update, incorporating further optimizations and refinements to keep the IP core up to date with changing technology and industry standards.

These releases showcase the commitment of Oregano Systems to continuously enhance and refine their 8051 IP Core to meet the evolving needs of SoC designers and maintain compatibility with the 8051 architecture.

Oregano Systems provides two informative demo designs to illustrate the usage of the 8051 IP core. These demo designs are flexible and can be extended to suit the specific requirements of your project. Each example is packaged as a ZIP file, including all necessary components such as VHDL code, C-code, design setups, and comprehensive documentation in PDF format.

  1. 8051 IP on an Altera Cyclone Nios Board:
    • This demo design is tailored for implementation on the popular Altera Cyclone Nios evaluation board, showcasing the integration of the 8051 IP core.
    • It provides insights into hardware setup, software compilation, and the loading of program code into the 8051 IP core’s program ROM.


    • 8051 IP Core: Source Files – Cyclone Nios Board Implementation
    • 8051 IP Core: User Guide – Cyclone Nios Board Implementation
  2. 8051 Boot Loader Demo Design:
    • This sample design introduces a straightforward boot loader that resides in the processor’s on-chip ROM. The actual program is downloaded during runtime via the serial interface into the program RAM.


    • 8051 IP Core: Source Files – Boot Loader Demo Design
    • 8051 IP Core: User Guide – Boot Loader Demo Design

These demo designs provide valuable insights into the practical implementation and utilization of the 8051 IP core, offering a foundation for customization to meet the specific needs of your project.


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8051 IP Core

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